The present invention relates to multibit arithmetic logic units (ALU's), more specifically, multibit adders-subtractors (A/S), having fast carry-look-ahead (CLA) systems, and particularly to a CLA system designed to speed-up the execution of arithmetical operations.
As known, most of the time required by ALU's to execute arithmetical operations is due to the carry propagation delay via the CLA system. Many systems involving various CLA techniques have been devised to reduce this delay. These known techniques, however, require the introduction of additional circuitries whose complexity increases inordinately after a certain number of bits. These additional bits contribute additional propagation delay (PD) per each additional CLA level, which is a primary limitation in speeding-up the operation of extended-length ALU's.